Layout-based wafer defect identification and classification using separately generated predicted images and predicted layout designs

Abstract

This application discloses a scanning electron microscope system to capture an image of an electronic device manufactured according to a layout design describing the electronic device, and a computing system to generate a predicted image of the electronic device using the layout design. The predicted image corresponds to an expected image of the electronic design system captured by the scanning electron microscope system. The computing system identifies manufacturing defects present in the electronic device based on differences between the predicted image of the electronic device and the captured image of the electronic device, and utilizes the captured image of the electronic device to classify the manufacturing defects identified based on the predicted image of the electronic device from the layout design. The computing system can generate a manufacturing defect report identifying the manufacturing defects used to perform repair of the electronic device or modification of the layout design.