The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Jul. 30, 2020
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Joel Goergen, Soulsbyville, CA (US);

Sam Gupta, Costa Mesa, CA (US);

Dylan Thomas Walker, Austin, TX (US);

Chirag K. Shroff, Cary, NC (US);

Christopher Shannon Gourley, Sweetwater, TN (US);

Rachel Marie Weeks, Knoxville, TN (US);

Elizabeth Ann Kochuparambil, Morgan Hill, CA (US);

Ronald Lee Shaffer, II, Knoxville, TN (US);

Assignee:

CISCO TECHNOLOGY, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/31 (2013.01); G06V 20/00 (2022.01); G06V 20/80 (2022.01); H04L 9/32 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
G06F 21/31 (2013.01); G06V 20/80 (2022.01); H04L 9/3234 (2013.01); H04L 9/3263 (2013.01); H05K 1/0269 (2013.01); H05K 1/0306 (2013.01); G06V 20/95 (2022.01); H05K 2203/16 (2013.01);
Abstract

An apparatus includes a printed circuit board (PCB) that includes a woven glass laminate layer. The woven glass laminate layer includes a plurality of glass bundles woven together, where a marker structure including at least one marker is defined within the woven glass laminate layer. A security chip is coupled with the PCB and includes memory that stores an authentication identifier of the PCB, where the authentication ID includes a representation of the marker structure.


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