The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Sep. 25, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Udo Ausserlechner, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01L 1/22 (2006.01); G01L 1/18 (2006.01);
U.S. Cl.
CPC ...
G01L 1/2281 (2013.01); G01L 1/18 (2013.01); G01L 1/2293 (2013.01);
Abstract

A semiconductor circuit arrangement includes a substrate, at least two first stress-sensitive elements in a first region of the substrate and at least two second stress-sensitive elements in a second region of the substrate. The first stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the first region. The second stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the second region. The semiconductor circuit arrangement includes a measuring circuit configured, based on the respective electrical characteristics of the first stress-sensitive elements and of the second stress-sensitive elements, to determine a stress difference between the first components in the first and second regions and a stress difference between the second components in the first and second regions.


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