The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Sep. 14, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangho Lee, Suwon-si, KR;

Kihyun Kim, Suwon-si, KR;

Sangyong Park, Suwon-si, KR;

Kwanghyun Baek, Suwon-si, KR;

Seungjae Baek, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H05K 1/181 (2026.01); H10W 70/68 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H05K 1/181 (2013.01); H10W 70/68 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H05K 2201/10015 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10704 (2013.01); H05K 2201/10734 (2013.01); H05K 2201/10962 (2013.01); H10W 90/724 (2026.01);
Abstract

A package device is provided. The package device includes a substrate, a plurality of upper lands disposed on one surface of the substrate, a plurality of upper solder balls disposed on the plurality of upper lands, a die connected to the plurality of upper solder balls, a plurality of lower lands disposed on the other surface of the substrate, a plurality of lower solder balls disposed on some of the plurality of lower lands, and a capacitor connected to the lower lands on which the plurality of lower solder balls are not disposed among the plurality of lower lands, provided on an opposite side of the die, and including a height greater than the height of the plurality of lower solder balls.


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