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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12667007 B1

PDFFull Text
Date of Patent:
Jun. 23, 2026

Filed:

Oct. 19, 2022

Diode and bipolar junction transistor for 3d sfet with bspdn structure

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byounghak Hong, Albany, NY (US);

Wookhyun Kwon, Hwaseong-si, KR;

Jaehong Lee, Albany, NY (US);

Assignee:

SAMSUNG ELECTRONICS CO., LTD., , KR;

Attorney:

Myers Bigel, P.A.

Primary Examiner:

Dale E Page

Assistant Examiner:

Wilner Jean Baptiste

Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/528 (2006.01); H10D 88/00 (2025.01); H10D 89/60 (2025.01); H10W 20/41 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10D 88/00 (2025.01); H10D 89/711 (2025.01); H10W 20/427 (2026.01);
Abstract

A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.

Find Patent Forward Citations

Hong, Byounghak. (2026). Diode and bipolar junction transistor for 3d sfet with bspdn structure (U.S. Patent No. 12667007). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12667007

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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