The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Aug. 02, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jinho Park, Suwon-si, KR;

Hyerim Jwa, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/10 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/10 (2023.02); G11C 11/161 (2013.01); H10B 61/22 (2023.02); H10N 50/80 (2023.02); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01);
Abstract

A variable resistance memory device includes a substrate at least partially defining a peripheral area surrounding a cell area, a lower insulating layer in the cell and peripheral areas, a magnetic tunnel junction structure in the cell area, a capping layer conformally covering both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell area, a buried insulating layer burying the magnetic tunnel junction structure in the cell area, and an interlayer insulating layer covering a second portion of the lower insulating layer in the peripheral area. The buried and interlayer insulating layers include respective tapered contact surfaces. Respective vertical contact surfaces of the buried and interlayer insulating layers contact each other at an interface extending in the vertical direction from a top surface of the second portion of the lower insulating layer in the peripheral area to a first height.


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