Vertical pn connection in multi-stack semiconductor device

Abstract

A multi-stack semiconductor device includes: a substrate; a lower field-effect transistor including a lower channel structure, a lower gate structure surrounding the lower channel structure, and 1and 2source/drain regions; and an upper field-effect transistor, on the lower field-effect transistor, including an upper channel structure, an upper gate structure surrounding the upper channel structure, and 3and 4source/drain regions vertically above the 1and 2source/drain regions, respectively, wherein the 1source/drain region is connected to one of a positive voltage source and a negative voltage source, and the 3source/drain region is connected to the other of the positive voltage source and the negative voltage source, and wherein a top portion of the 2source/drain region and a bottom portion the 4source/drain region are connected to each other.