The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Sep. 30, 2022
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Harsh Naik, El Segundo, CA (US);

Timothy Henson, Mount Shasta, CA (US);

Honghai He, Redondo Beach, CA (US);

Robert Haase, San Pedro, CA (US);

Ashita Mirchandani, Torrance, CA (US);

Alireza Mojab, El Segundo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H02M 1/088 (2006.01); H10D 30/65 (2025.01); H10D 64/00 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 30/20 (2026.01); H10P 30/22 (2026.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H02M 1/088 (2013.01); H10D 30/0289 (2025.01); H10D 30/658 (2025.01); H10D 64/117 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10P 30/204 (2026.01); H10P 30/21 (2026.01); H10P 30/22 (2026.01);
Abstract

A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.


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