The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jan. 07, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Benjamin D. Briggs, Waterford, NY (US);

Kisik Choi, Watervliet, NY (US);

Brent A. Anderson, Jericho, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 64/251 (2025.01);
Abstract

Methods for fabricating a semiconductor device are provided. The method can include forming a conductive material layer on a semiconductor device, the semiconductor device including at least two gate structures and at least two source/drain surfaces of at least two source/drain regions, wherein an interlevel dielectric layer separates each of the at least two gate structures from each of the at least two source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacting the at least two source/drain surfaces and forming at least two conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer, forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer includes an up-via and forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.


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