The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Mar. 30, 2022
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiayu He, Beijing, CN;

Yan Qu, Beijing, CN;

Liping Lei, Beijing, CN;

Ce Ning, Beijing, CN;

Zhengliang Li, Beijing, CN;

Hehe Hu, Beijing, CN;

Jie Huang, Beijing, CN;

Nianqi Yao, Beijing, CN;

Kun Zhao, Beijing, CN;

Feifei Li, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6739 (2025.01); G02F 1/1368 (2013.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01);
Abstract

There is provided a metal oxide thin film transistor, including: a substrate and a metal oxide semiconductor layer on the substrate; a gate and a gate insulating layer between the substrate and the metal oxide semiconductor layer; the gate insulating layer includes a first silicon nitride layer, a second silicon nitride layer and a first silicon oxide layer which are stacked; the first silicon oxide layer is in contact with the metal oxide semiconductor layer, and two surfaces of the second silicon nitride layer are in contact with the first silicon nitride layer and the first silicon oxide layer, respectively; a content of hydrogen atoms of at least a partial region of the second silicon nitride layer is less than 30% of a content of hydrogen atoms of at least a partial region of the first silicon nitride layer. An array substrate and a display device are further provided.


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