The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Sep. 29, 2022
Icp Technology Co., Ltd., Taoyuan, TW;
Sentec E&e Co., Ltd., Taoyuan, TW;
Ho-Chieh Yu, Taoyuan, TW;
Chen-Cheng-Lung Liao, Taoyuan, TW;
Chun-Yu Lin, Taoyuan, TW;
Jason an Cheng Huang, Taoyuan, TW;
Chih-Chuan Liang, Taoyuan, TW;
Kun-Tzu Chen, Taoyuan, TW;
Nai-His Hu, Taoyuan, TW;
Liang-Yo Chen, Taoyuan, TW;
ICP Technology Co., LTD., Taoyuan, TW;
SENTEC E&E CO., LTD., Taoyuan, TW;
Abstract
Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.