The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Oct. 23, 2024
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Laurent Gambus, Cuverville, FR;

Nicolas Constantinidis, Creserons, FR;

Rafael Luciano Radin, Caen, FR;

Philippe Christian Belin, Mezidon vallee d'auge, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/199 (2006.01); G06F 1/12 (2006.01); H03L 7/187 (2006.01);
U.S. Cl.
CPC ...
H03L 7/187 (2013.01); G06F 1/12 (2013.01); H03L 7/199 (2013.01); H03L 2207/18 (2013.01);
Abstract

A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers includes synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases including a common phase. The global reset is applied to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase.


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