High-speed four-phase twenty-five percent duty clock generator

Abstract

A four-phase clock generator includes a four-stage ring including four MOS transistors of a first conductivity type, each configured in a common-source arrangement and interconnected in a ring topology to sequentially and cyclically de-assert phases of a four-phase output clock, respectively; a first alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the first phase and the third phase of the four-phase output clock; a second alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the second phase and the fourth phase of the four-phase output clock; and an assertion network having four MOS transistors of a second conductivity type configured to sequentially and cyclically assert phases of the output clock in accordance with four gated clock signals generated by alternately gating phases of input and output clocks.