Page buffer circuit and memory device including a page buffer circuit

Abstract

A memory device includes a memory cell array, a plurality of page buffer units connected to the memory cell array and connected in common to a combined sensing node, and a plurality of cache latches respectively corresponding to the plurality of page buffer units, the plurality of cache latches including a first cache latch and a second cache latch connected in common to the combined sensing node. In a first section of a data dumping operation on the first cache latch, first and second tri-state inverters included in the first cache latch are enabled to transmit data to the first cache latch, and third and fourth tri-state inverters included in the second cache latch are disabled. In a second section of the data dumping operation on the first cache latch, the third and fourth tri-state inverters are sequentially enabled to restore data previously stored in the second cache latch.