Semiconductor memory device performing multi-bit programming using sequential write operations with reduced latch count

Abstract

A semiconductor memory device includes bit lines, memory cells that are respectively connected to the bit lines, sense amplifier units that are respectively connected to the bit lines, and each of which includes m latch circuits, and a logic control circuit configured to input data to the m latch circuits and control a write operation on each of the memory cells using the data input to the m latch circuits. The logic control circuit executes an operation to write n bits to each of the memory cells, where n is 2 or more and greater than m, by executing a plurality of write operations, including a first write operation executed on the memory cells by inputting first m bits of data to the m latch circuits, and a second write operation executed on the memory cells by inputting second m bits of data to the m latch circuits.