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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12665024 B1

PDFFull Text
Date of Patent:
Jun. 23, 2026

Filed:

Dec. 13, 2023

Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating

Applicant:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Inventor:

Yuniarto Widjaja, Cupertino, CA (US);

Assignee:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:

Omar F Mojaddedi

Int. Cl.
CPC ...
G11C 11/404 (2006.01); G11C 11/56 (2006.01); G11C 14/00 (2006.01); G11C 16/06 (2006.01); H10B 12/00 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0018 (2013.01); G11C 11/404 (2013.01); G11C 11/565 (2013.01); G11C 16/06 (2013.01); H10B 12/00 (2023.02); H10B 12/20 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/68 (2025.01); H10D 30/681 (2025.01); H10D 30/6892 (2025.01); H10D 30/711 (2025.01); H10D 62/115 (2025.01); H10D 64/661 (2025.01); G11C 16/0416 (2013.01); G11C 16/0433 (2013.01); G11C 2211/4016 (2013.01);
Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

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Widjaja, Yuniarto. (2026). Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating (U.S. Patent No. 12665024). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12665024

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