The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Aug. 29, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tsuneo Inaba, Kamakura Kanagawa, JP;

Takayuki Miyazaki, Tokyo, JP;

Shinji Miyano, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4099 (2013.01);
Abstract

A memory device includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end. The fourth end is coupled to the second end. The plate line is coupled to the third end. The bit line is coupled to the first end. A second voltage lower than a first voltage is applied to the plate line during a first period over which the first voltage is applied to the gate. A fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period over which a third voltage lower than the first voltage is applied to the gate.


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