Decoding method and decoder device used in flash memory controller capable of reducing design complexity and circuit costs

Abstract

A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vof a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vinto the direction of variable node Vto generate an estimated syndrome value of variable node V; rotating the syndrome value of variable node Vinto the direction of variable node Vto generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.