The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Aug. 30, 2022
Applicant:

Amcad Engineering, Limoges, FR;

Inventors:

Christophe Charbonniaud, Chabrignac, FR;

Nicolas Labrousse, Aixe-sur-Vienne, FR;

Maxime Faure, Limoges, FR;

Assignee:

AMCAD ENGINEERING, Limoges, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01);
U.S. Cl.
CPC ...
G01R 31/2607 (2013.01); G01R 31/2601 (2013.01);
Abstract

A method for characterizing in pulse-mode a III-V semiconductor transistor () utilizes an associated test bench (). An RF pre-pulse is applied to the gate (a) of the transistor () with a power level NRF defined according to a first predetermined law of variation so as to fix the charge state of the traps in the transistor (). Then a first DC pulse and a second DC pulse are applied to the gate (a) and to the drain (b) of the transistor (), respectively. The first DC pulse and the second DC pulse have a first DC level N1 and a second DC level N2, respectively, defined according to a second predetermined law of variation.


Find Patent Forward Citations

Charbonniaud, Christophe. (2026). Method for characterizing in pulse mode a iii-v semiconductor transistor and associated test bench (U.S. Patent No. 12663458). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12663458

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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