The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jan. 20, 2022
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Jun Furukawa, Yamagata, JP;

Kazuya Suzuki, Yamagata, JP;

Keiichiro Mori, Saga, JP;

Takahiro Nagasawa, Saga, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 21/95 (2006.01); C30B 29/06 (2006.01); C30B 33/00 (2006.01); G01B 11/30 (2006.01); G01N 21/84 (2006.01); G01N 21/88 (2006.01); G01N 21/956 (2006.01); H10P 74/20 (2026.01);
U.S. Cl.
CPC ...
G01N 21/9501 (2013.01); C30B 29/06 (2013.01); C30B 33/00 (2013.01); G01B 11/30 (2013.01); G01N 21/9505 (2013.01); G01N 21/95607 (2013.01); H10P 74/20 (2026.01); H10P 74/203 (2026.01); G01N 2021/8477 (2013.01); G01N 2021/8864 (2013.01); G06T 2207/30148 (2013.01);
Abstract

A method of evaluating a silicon single-crystal ingot, the method including cutting out three or more plural silicon wafers from the ingot to be evaluated; mirror polishing the plural silicon wafers to yield silicon mirror-surface wafers; processing the plural silicon mirror polished wafers into silicon epitaxial wafers through formation of an epitaxial layer on the mirror polished surfaces; acquiring light point defect maps of the epitaxial layer surfaces of the plural silicon epitaxial wafers with a laser surface inspection device; and creating an overlay map. In a case where a light point defect group in which three or more light point defects are linearly distributed is not confirmed in the overlay map, a region, from which the plural silicon wafers have been cut out, in the silicon single-crystal ingot to be evaluated, is estimated not to be a region in which a twin has occurred.


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