The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Jun. 27, 2023
Applicant:
Huawei Technologies Co., Ltd., Shenzhen, CN;
Inventors:
Assignee:
HUAWEI TECHNOLOGIES CO., LTD., Shenzhen, CN;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 72/00 (2026.01); H10W 90/20 (2026.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 90/20 (2026.01); H10W 20/023 (2026.01); H10W 20/0253 (2026.01); H10W 72/877 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/732 (2026.01);
Abstract
A chip stacking structure includes a plurality of chips that are sequentially stacked and a first redistribution layer arranged on an active side of each chip. The plurality of chips include a first chip and a second chip that are located on an outermost side. Passive sides of the first chip and the second chip both face an outer side, and the chip stacking structure further includes a second redistribution layer arranged on the passive side of the first chip or the second chip. The second redistribution layer is electrically connected to at least one first redistribution layer through a first via hole.