The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jun. 28, 2023
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Divya Madapusi Srinivas Prasad, Mountain View, CA (US);

Vignesh Adhinarayanan, Austin, TX (US);

Michael Ignatowski, Austin, TX (US);

Hyung-Dong Lee, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); G11C 11/4097 (2006.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); G11C 11/4097 (2013.01); H10W 90/20 (2026.01);
Abstract

Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.


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Prasad, Divya Madapusi Srinivas. (2026). 3d layout and organization for enhancement of modern memory systems (U.S. Patent No. 12660703). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12660703

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