The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Aug. 29, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jiwon Kim, Suwon-si, KR;

Jiyoung Kim, Suwon-si, KR;

Woosung Yang, Suwon-si, KR;

Sukkang Sung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); G11C 16/0483 (2013.01); H01L 25/0652 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 80/00 (2023.02); H01L 2225/06506 (2013.01);
Abstract

A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions and including a plate layer; gate electrodes spaced apart from each other in a first direction; channel structures passing through the gate electrodes; gate separation regions extending in a second direction; first and second upper isolation regions dividing an upper gate electrode into first, second and third sub-gate electrodes between adjacent gate separation regions; and contact plugs extending in the first direction, each of the first and second upper isolation regions has a region extending in a third direction, and the first sub-gate electrode has a first pad region having a first width and a second pad region having a second width narrower than the first width in a fourth direction, and the first sub-gate electrode is connected to one of the contact plugs.


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