The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Oct. 31, 2022
Applicant:

Mediatek Inc., Hsinchu City, TW;

Inventors:

Kin-Hooi Dia, Hsinchu City, TW;

Ho-Chieh Hsieh, Hsinchu City, TW;

Hsing-I Tsai, Hsinchu City, TW;

Assignee:

MEDIATEK INC., Hsinchu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); H10D 84/85 (2025.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); H10D 84/85 (2025.01); H03K 19/0013 (2013.01); H03K 19/017 (2013.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.


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