The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jun. 14, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jinwoo Lee, Seoul, KR;

Chunyub Park, Busan, KR;

Sutae Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01326 (2026.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01);
Abstract

A method of manufacturing a semiconductor device may include forming a hardmask layer on gate lines and intergate insulating portions alternately arranged; respectively forming mandrel lines on regions of the hardmask layer, corresponding to every other one of the intergate insulating portions; conformally forming a spacer material layer, having a thickness corresponding to a width of the gate lines, on the hardmask layer; forming a mandrel material layer on the spacer material layer; removing a portion of the mandrel material layer to expose portions of the spacer material layer on an upper surface and a side surface of the mandrel line; removing the exposed portions of the spacer material layer to provide the mandrel lines and stacked mandrel patterns; and forming an opening in the hardmask layer, which exposes a gate-cut region of the gate lines, using the mandrel lines and the stacked mandrel patterns as a mask.


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