The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Apr. 18, 2023
Applicant:
Infineon Technologies Austria Ag, Villach, AT;
Inventors:
Stefan Tegen, Dresden, DE;
Timothy Henson, Mount Shasta, CA (US);
Assignee:
Infineon Technologies Austria AG, Villach, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/60 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 30/601 (2025.01); H10D 30/0212 (2025.01); H10D 30/024 (2025.01); H10D 30/0297 (2025.01); H10D 30/6211 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 64/021 (2025.01); H10D 64/112 (2025.01); H10D 64/117 (2025.01); H10D 64/693 (2025.01);
Abstract
In an embodiment, a power transistor device includes a substrate formed of crystalline silicon and having a first surface and a second surface opposing the first surface. A field plate formed of polysilicon is electrically connected with the substrate. An interfacial silicon nitride layer is arranged between the polysilicon of the field plate and the crystalline silicon of the substrate.