The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Apr. 07, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junhyoung Kim, Seoul, KR;

Myunghun Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2026.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 21/76283 (2013.01); H01L 24/80 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80009 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/80379 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/0504 (2013.01); H01L 2924/0544 (2013.01); H01L 2924/059 (2013.01); H01L 2924/14511 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor device may include a first substrate structure including a plate layer, gate electrodes stacked on the plate layer, channel structures penetrating through the gate electrodes, and first bonding metal layers on the channel structures; and a second substrate structure connected to the first substrate structure, and including a substrate having active regions, device isolation layers in the substrate defining the active regions, circuit devices on one surface of the substrate, and second bonding metal layers connected to the first bonding metal layers, the device isolation layers including first device isolation layers and a second device isolation layer having different heights, and the active regions including first active regions spaced apart by the first device isolation layers and connected to each other by the substrate, and second active regions separated from the first active regions by the second device isolation layer.


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