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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12660196 B1

PDFFull Text
Date of Patent:
Jun. 16, 2026

Filed:

May. 02, 2023

Three-dimensional non-volatile memory device

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunmook Choi, Suwon-si, KR;

Jihong Kim, Suwon-si, KR;

Siyeon Cho, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Matthew E Warren

Int. Cl.
CPC ...
H10B 51/30 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/50 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 53/10 (2023.01); H10B 53/20 (2023.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 53/10 (2023.02); H10B 53/20 (2023.02); H10B 53/30 (2023.02);
Abstract

A three-dimensional non-volatile memory device includes horizontal word lines separated from each other in a vertical direction, horizontal ferroelectric layers arranged among the horizontal word lines, the horizontal ferroelectric layers including upper horizontal ferroelectric layers and lower horizontal ferroelectric layers, vertical ferroelectric layers contacting side walls of the horizontal ferroelectric layers and extending in the vertical direction, a semiconductor pillar passing through the horizontal word lines in the vertical direction, and a channel region between the horizontal word lines and the semiconductor pillar, wherein the upper horizontal ferroelectric layers and the lower horizontal ferroelectric layers are separated from each other by an air gap in the vertical direction.

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