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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12660187 B1

PDFFull Text
Date of Patent:
Jun. 16, 2026

Filed:

Aug. 16, 2023

Semiconductor memory devices and electronic systems including the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Beyong Hyun Koh, Suwon-si, KR;

Ho Jin Kim, Suwon-si, KR;

Geun Won Lim, Suwon-si, KR;

Jung Ho Lee, Suwon-si, KR;

Hyun Gun Jang, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Attorney:

Wolf, Greenfield & Sacks, P.C.

Primary Examiner:

William B Partridge

Assistant Examiner:

Chevy J Boegel

Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10D 62/13 (2025.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 5/063 (2013.01); G11C 16/0483 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10D 62/151 (2025.01); H10W 20/435 (2026.01);
Abstract

A semiconductor memory device comprises a substrate; a mold structure on the substrate; a plurality of channel structures extending in the mold structure; a source layer and a source sacrificial layer between the substrate and the mold structure, wherein the source sacrificial layer is spaced apart from the source layer; and a source support layer on the source layer and the source sacrificial layer, wherein the source support layer is between the source layer and the source sacrificial layer, wherein an upper surface of the source support layer includes first and second portions extending parallel to the substrate, and a third portion that connects the first and second portions, wherein a vertical distance from an upper surface of the source layer to the first portion is smaller than a vertical distance from an upper surface of the substrate to the second portion.

Find Patent Forward Citations

Koh, Beyong. (2026). Semiconductor memory devices and electronic systems including the same (U.S. Patent No. 12660187). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12660187

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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