The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

May. 25, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jung Shik Jang, Icheon-si, KR;

In Su Park, Icheon-si, KR;

Won Geun Choi, Icheon-si, KR;

Jung Dal Choi, Icheon-si, KR;

Rho Gyu Kwak, Icheon-si, KR;

Seok Min Choi, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 43/10 (2023.01); H10B 43/30 (2023.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10W 20/435 (2026.01);
Abstract

A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.


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