The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Sep. 19, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Igor Gutman, Hod HaSharon, IL;

Elias Dagher, Laguna Niguel, CA (US);

Hua Wang, Basking Ridge, NJ (US);

Behnam Sedighi, La Jolla, CA (US);

Seyed Arash Mirhaj, Poway, CA (US);

Tao Luo, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); G06N 3/08 (2023.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0626 (2013.01); G06N 3/08 (2013.01); H03M 1/1245 (2013.01);
Abstract

A training signal generator for forming an input signal for an ADC-under-test includes a one-bit DAC and an analog low-pass filter. The one-bit DAC converts a binary sequence into a DAC output signal that is then filtered by the analog low-pass filter to form an ADC input signal. The ADC-under-test converts the ADC input signal into an ADC output signal. A digital low-pass filter converts the binary sequence into a plurality of samples. A digital signal processing system processes the plurality of samples and the ADC output signal to form an estimate of the ADC input signal. An ADC linearizer may then be trained to characterize a non-linear impairment of the ADC-under-test responsive to a comparison of the estimate of the ADC input signal and the ADC output signal.


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