The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Aug. 19, 2022
Applicant:

Alpha and Omega Semiconductor International Lp, Toronto, CA;

Inventors:

Shekar Mallikarjunaswamy, San Jose, CA (US);

Jongjib Kim, Santa Clara, CA (US);

Son Tran, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/011 (2006.01); H03K 17/687 (2006.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H03K 3/011 (2013.01); H03K 17/687 (2013.01); H10D 30/65 (2025.01); H10D 62/109 (2025.01); H10D 62/393 (2025.01); H10D 64/112 (2025.01);
Abstract

A power device, circuit and method of making are described. The power device circuit includes a semiconductor substrate composition having a substrate layer of a first conductivity type wherein the first conductivity type is opposite a second conductivity type. Two or more lateral double diffused metal oxide semiconductor (LDMOS) devices are formed in the substrate layer and integrated into an isolation region of a high voltage well, wherein each LDMOS is isolated from a power device substrate area by an isolator structure formed from the substrate layer. One or more boost structures are integrated into the isolation region of the high voltage well wherein the one or more boost structures are in contact with the high voltage well and extend into the isolation region of the high voltage well.


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