The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Oct. 18, 2021
3m Innovative Properties Company, St. Paul, MN (US);
Jinwook Kim, Hwaseong-si, KR;
Seong-Woo Woo, Gwangju-si, KR;
3M Innovative Properties Co., St. Paul, MN (US);
Abstract
The present disclosure relates to a coil and an electrical system. According to an embodiment of the present disclosure, specifically, there is provided a coil including: main coil surfaces which face each other and are substantially planar; and a multilayer film which is wound to form a plurality of loops which are substantially concentric, wherein the plurality of loops include an innermost loop including a first longitudinal end of the multilayer film, a first intermediate loop, and an outermost loop including a second longitudinal end of the multilayer film, wherein the multilayer film includes a first electrical conduction layer, a second magnetic conduction layer, and a third adhesive layer, wherein the second magnetic conduction layer is coupled with the first electrical conduction layer by the third adhesive layer, wherein the first electrical conduction layer, the second magnetic conduction layer, and the third adhesive layer have widths and lengths which are substantially coextensive with one another, such that the main coil surfaces which are substantially planar include corresponding end surfaces of the first electrical conduction layer, the second magnetic conduction layer, and the third adhesive layer, respectively, wherein the first intermediate loop is disposed between the innermost loop and the outermost loop, wherein a first electro-conductive terminal is terminated on the first electrical conduction layer of the first intermediate loop.