The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Mar. 27, 2024
Memory device with vertical wiring between semiconductor layers and memory system including the same
Samsung Electronics Co., Ltd., Suwon-si, KR;
Daehyeon Kwon, Suwon-si, KR;
Donggeon Kim, Suwon-si, KR;
Bokyeon Won, Suwon-si, KR;
Selyung Yoon, Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.