Storage device, memory controller, non-volatile memory device, and method of operating memory controller for controlling data output timing

Abstract

A storage device includes non-volatile memory dies, and a memory controller that outputs a first data output command address packet and receives first data. The memory controller receives the first data from a first non-volatile memory die through a data bus, and sequentially outputs a second data output command packet that instructs a second non-volatile memory die among the plurality of non-volatile memory dies to output second data, a second select chip enable packet that selects the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die. The second select chip enable packet includes a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first delay information for delaying an output point in time of the second data.