The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Jul. 21, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Umberto Ferlito, Catania, IT;

Michele Vaiana, San Giovanni la Punta, IT;

Giuseppe Bruno, Paterno', IT;

Alfio Dario Grasso, Riposto, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/565 (2006.01); G05F 1/575 (2006.01); G05F 3/26 (2006.01);
U.S. Cl.
CPC ...
G05F 1/565 (2013.01); G05F 1/575 (2013.01); G05F 3/262 (2013.01);
Abstract

A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.


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