The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Jul. 28, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Nagesh Vodrahalli, Los Altos, CA (US);

Chih-Yang Li, Menlo Park, CA (US);

Shrikar Bhagath, San Jose, CA (US);

Narayanan Terizhandur V, Bothell, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 90/00 (2026.01); H10W 42/20 (2026.01); H10W 72/50 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 42/271 (2026.01); H10W 72/5445 (2026.01); H10W 90/24 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01); H10W 90/755 (2026.01);
Abstract

A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.


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