The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2026
Filed:
Aug. 20, 2024
Vanguard International Semiconductor Corporation, Hsinchu, TW;
PO-Yuan Tang, Hsinchu City, TW;
Yang-Sen Yeh, Baoshan Township, TW;
Yu-Chuan Chang, Hsinchu City, TW;
Hsuan-Chi Su, Qionglin Township, TW;
Chung-Wei Tsai, Zhubei City, TW;
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Abstract
A logic circuit including a first PMOS transistor, a second PMOS transistor, and an NMOS transistor is provided. The first PMOS transistor is coupled to an input-output pad. The second PMOS transistor is coupled to the first PMOS transistor in series between the input-output pad and an output terminal and receives a first input signal. The NMOS transistor is coupled to the second PMOS transistor. The voltage of the bulk of the first PMOS transistor is a first floating level. The voltage of the bulk of the second PMOS transistor is a second floating level.