Duty cycle correction circuit

Abstract

A duty cycle correction circuit includes a phase adjustment circuit, a divider circuit, a phase difference detection circuit, and a duty control circuit. The phase adjustment circuit adjusts a duty cycle of a first input clock signal according to a plurality of control codes to generate a duty corrected clock signal. The divider circuit divides the duty corrected clock signal to generate a plurality of multi-phase clock signals. The phase difference detection circuit detects phase differences between the plurality of multi-phase clock signals to generate detection signals. The duty control circuit detects a bang-bang state of the duty corrected clock signal in accordance with the detection signals, changes values of the plurality of control codes by a first unit in accordance with the detection signals until the bang-bang state is detected, and adjusts the value of the plurality of control codes by a second unit smaller than the first unit when the bang-bang state is detected.