Controller configured to control memory device, operation method of controller, and storage device including memory device and controller

Abstract

Disclosed is an operation method of a controller which communicates with a plurality of memory devices. The method includes receiving a first reception signal, a second reception signal, and a data strobe signal, respectively, generating a first delay signal by performing first and second per-pin delay locked loop (ppDLL) operations on the first and second reception signals based on a rising edge of the data strobe signal, respectively, and generating first and second correction signals by performing first and second per-pin duty cycle correction (ppDCC) operations on the first and second delay signals based on a falling edge of the data strobe signal, respectively. Rising edges of the first and second correction signals are aligned with the rising edge of the data strobe signal, and first and second falling edges of the first correction signals are aligned with the falling edge of the data strobe signal.