The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jul. 06, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Youngdeuk Kim, Suwon-si, KR;

Heejung Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2026.01); H10W 40/22 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/655 (2026.01); H10W 70/68 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 40/22 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/121 (2026.01); H10W 70/655 (2026.01); H10W 70/682 (2026.01); H10W 72/877 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes a package substrate including a substrate cavity, the substrate cavity extending from an upper surface of the package substrate toward a lower surface of the package substrate, a wiring interposer attached to the package substrate, a memory semiconductor structure attached to a lower surface of the wiring interposer, at least a portion of the memory semiconductor structure art being accommodated in the substrate cavity, a logic semiconductor chip attached to an upper surface of the wiring interposer, a conductive spacer spaced apart from the logic semiconductor chip in a horizontal direction, the conductive spacer being attached to the upper surface of the wiring interposer and overlapping the memory semiconductor structure in a vertical direction, and a heat dissipation member over the logic semiconductor chip and the conductive spacer.


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Kim, Youngdeuk. (2026). Semiconductor package (U.S. Patent No. 12648490). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12648490

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