The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Oct. 18, 2022
Applicant:

Institute of Semiconductors, Guangdong Academy of Sciences, Guangzhou, CN;

Inventors:

Yingqiang Yan, Guangzhou, CN;

Chuan Hu, Guangzhou, CN;

Yunzhi Ling, Guangzhou, CN;

Wei Zheng, Guangzhou, CN;

Zhitao Chen, Guangzhou, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H05K 1/181 (2026.01); H05K 3/303 (2026.01); H10W 70/05 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H05K 1/181 (2013.01); H05K 3/303 (2013.01); H10W 70/093 (2026.01); H10W 70/095 (2026.01); H10W 74/017 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H05K 2201/10522 (2013.01); H10W 90/724 (2026.01); H10W 90/794 (2026.01);
Abstract

Provided are a fan-out package structure and a manufacturing method thereof. The fan-out package structure provided in the embodiments of the present disclosure, and the fan-out package structure obtained by the manufacturing method provided in the embodiments of the present disclosure have an inter-chip fine interconnection line between functional surfaces of chips, so that fine interconnection pin pads of adjacent chips form electrical interconnection.


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