The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Mar. 24, 2022
Applicants:

Hyundai Motor Company, Seoul, KR;

Kia Corporation, Seoul, KR;

Inventors:

Kyoung-Kook Hong, Hwaseong-si, KR;

Su-Bin Kang, Seongnam-si, KR;

Young-Seok Kim, Seongnam-si, KR;

Assignees:

HYUNDAI MOTOR COMPANY, Seoul, KR;

KIA CORPORATION, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/373 (2006.01); H10W 40/25 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 40/255 (2026.01); H10W 72/01336 (2026.01); H10W 72/01351 (2026.01); H10W 72/073 (2026.01); H10W 72/07331 (2026.01); H10W 72/07332 (2026.01); H10W 72/07352 (2026.01); H10W 72/07354 (2026.01); H10W 72/327 (2026.01); H10W 72/347 (2026.01); H10W 72/352 (2026.01); H10W 72/952 (2026.01); H10W 90/734 (2026.01);
Abstract

The present disclosure provides a method for manufacturing a double-sided cooling type power module including separately patterning a bonding material on a base film into two regions, positioning a semiconductor chip on the patterned bonding material, transferring the patterned bonding material to one surface of the semiconductor chip by pressurizing the semiconductor chip, positioning the bonding material of the semiconductor chip on an upper electrode layer formed on an upper substrate to be in contact with the upper electrode layer, and sintering an upper bonding layer by pressurizing and heating the semiconductor chip. According to the present disclosure, it is possible to separately dispose the bonding material on each of gate and source electrode parts on an upper portion of the chip even without protrusion to directly bond the chip and the substrate.


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