The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Aug. 14, 2023
Applicant:

United Semiconductor (Xiamen) Co., Ltd., Xiamen, CN;

Inventors:

Shouguo Zhang, Singapore, SG;

Yongbo Xu, Xia Men, CN;

Wen Yi Tan, Xiamen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10P 14/44 (2026.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 64/017 (2025.01); H10D 84/0172 (2025.01); H10P 14/44 (2026.01); H10W 20/056 (2026.01); H10W 20/074 (2026.01);
Abstract

A method for fabricating a semiconductor structure is disclosed. A substrate having a dielectric layer thereon and a gate trench formed in the dielectric layer is prepared. The substrate is subjected to a physical vapor deposition (PVD) process in a physical vapor deposition chamber equipped with an auto capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and on an interior surface of the gate trench. The PVD process comprises: (i) tuning the auto capacitance tuner to provide positive radio frequency (RF) bias to the substrate in the PVD chamber for a first time period; and (ii) subsequently tuning the auto capacitance tuner to provide negative RF bias to the substrate in the PVD chamber for a second time period.


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