The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jul. 08, 2019
Applicant:

University of Copenhagen, Copenhagen K, DK;

Inventors:

Thomas Sand Jespersen, Virum, DK;

Jesper Nygård, København Ø, DK;

Damon Carrad, København N, DK;

Martin Bjergfelt, Frederiksberg, DK;

Assignee:

University of Copenhagen, Copenhagen K, DK;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10N 60/01 (2023.01); H10D 48/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/123 (2025.01); H10N 60/0604 (2023.02); H10N 60/0632 (2023.02); H10D 48/383 (2025.01); H10N 60/0941 (2023.02);
Abstract

The present disclosure further relates to nanostructures, in particular hybrid nanostructures with patterned growth of various layers for use in nanoscale electronic devices, such as hybrid semiconductor nanostructures with patterned growth and/or deposition of superconducting material for use in quantum devices. The presently disclosed method can be utilized for in-situ manufacturing of nanoscale electronic devices that have not been contaminated by ex-situ processes. One embodiment relates to a method for manufacturing a substrate for growth of crystalline nanostructures, the method comprising the steps of: depositing one or more layers of a crystal growth compatible dielectric material, such as silicon oxide, in a predefined pattern on the surface of a crystal growth compatible substrate to create a predefined etch pattern of said crystal growth compatible material, and selectively etching the substrate surface around said etch pattern to provide at least one under-etched platform which is vertically raised from the etched substrate surface.


Find Patent Forward Citations

Jespersen, Thomas. (2026). Method for manufacture of nanostructure electrical devices (U.S. Patent No. 12648196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12648196

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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