The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Feb. 16, 2023
Applicant:

Hon Young Semiconductor Corporation, Hsinchu City, TW;

Inventors:

Kuang-Hao Chiang, Hsinchu City, TW;

Yan-Ru Chen, Hsinchu City, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/0291 (2025.01); H10D 62/107 (2025.01);
Abstract

A semiconductor device includes a substrate, an epitaxial layer, a well region, a current spreading layer, a source region, a base region and a gate layer. The epitaxial layer is on the substrate. The well region is in the epitaxial layer. The current spreading layer is in the epitaxial layer and below the well region. The current spreading layer includes a plurality of the first doped regions and a plurality of the second doped regions, the first doped regions includes a plurality of dopants of the first semiconductor-type, the second doped regions includes a plurality of dopants of the second semiconductor-type, and the second semiconductor-type is different from the first semiconductor-type. The source region is in the well region. The base region is in the well region and adjacent to the source region. The gate layer is over the epitaxial layer.


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