The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Apr. 12, 2023
Applicant:

SK Hynix Inc., Icheon, KR;

Inventor:

Woo Tae Lee, Icheon, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10B 63/10 (2023.01);
U.S. Cl.
CPC ...
H10B 63/80 (2023.02); H10B 63/10 (2023.02);
Abstract

A semiconductor device may include: memory cells arranged in a first direction and a second direction intersecting the first direction; first capping patterns extending in the first direction and covering first sidewalls of the memory cells; second capping patterns extending in the second direction and covering second sidewalls of the memory cells; first gap-fill patterns each located between the second capping patterns adjacent in the first direction; second gap-fill patterns each located between the first gap-fill patterns adjacent in the second direction; and barrier layers each located between the second gap-fill patterns.


Find Patent Forward Citations

Lee, Woo. (2026). Semiconductor memory device with barrier layers between gap-fill patterns and method of manufacturing the same (U.S. Patent No. 12648151). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12648151

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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