The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Jan. 07, 2025
Baya Systems, Inc., Santa Clara, CA (US);
Honnahuggi Harinath Venkata Naga Ambica Prasad, Bengaluru, IN;
Narayana Sri Harsha Gade, Bangalore, IN;
Eric Norige, Santa Clara, CA (US);
BAYA SYSTEMS, INC., Santa Clara, CA (US);
Abstract
System and method for generating a Network on Chip (NoC) includes intaking a specification, where the specification includes, for each sub-NoC design, hierarchical topology and Control/Status Register (CSR) controllers of the each sub-NoC with locations thereof. Further, for each of the CSR controller in the sub-NoC, the sub-NoC design includes a set of CSR endpoints that is communicatively coupled to the each of the CSR controllers and ingress and egress points of a boundary of the each sub-NoC. The network definition is generated for the each sub-NoC design from computation of routes between the locations of each pair of the CSR controllers and the set of CSR endpoints that communicate via a routing graph defined from the hierarchical topology that is adjusted based on the ingress and egress points. NoCs may be generated based on the network definitions.