The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Feb. 13, 2024
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Angel C. Abusleme Hoffman, Round Rock, TX (US);
Agustin R. Campeny, Austin, TX (US);
John L. Melanson, Austin, TX (US);
CIRRUS LOGIC, INC., Austin, TX (US);
Abstract
Reduced delay and improved threshold tracking over PVT in a comparator input circuit and comparator are provided by circuits that include an inverter stage having a first complementary pair of transistors connected in a push-pull configuration. An input of the inverter stage is coupled to the gates of the first complementary pair of transistors, and an output of the inverter is coupled to the drains of the first complementary pair of transistors. The circuits also include one or more first degeneration transistors coupled between a source of one of the first complementary pair of transistors and a power supply rail of the circuit, and a reference circuit with an output coupled to one or more gates of the first degeneration transistors. The reference circuit controls the one or more first degeneration transistors to cause the inverter stage to have a threshold voltage equal to a threshold control voltage.