Memory device including sense amplifier and method of storing data thereof

Abstract

A memory device includes a memory cell array including memory cells, a single-ended bitline sense amplifier connected to the memory cells through a bitline and a complementary bitline, and electrically connected through one of the bitline or the complementary bitline in response to the memory cells being activated. A DSI circuit is configured to conditionally transmit complementary input data generated by inverting input data to the single-ended bitline sense amplifier in response to a first number of bits included in the input data having a first level greater than a second number of bits included in the input data having a second level, and a data inversion flag indicating that the input data is inverted, to the sense amplifier. The sense amplifier stores the complementary input data in the memory cell array and the data inversion flag in a specified partial area of the memory cell array.